1. Field of the Invention
The present invention relates to an analog-digital converter and relates in particular to a pipeline type analog-digital converter.
2. Description of Related Art
FIG. 12 is a diagram schematically illustrating an example of a typical configuration of an analog-digital converter (hereinafter to be abbreviated as “A/D converter” or “ADC”) of a pipeline type. Here, on a general configuration of a pipeline type A/D converter, description in Patent Document 1 and Non-patent Documents 1, 2 and the like, for example, is brought into reference.
With reference to FIG. 12, that pipeline type A/D converter comprises a first stage (1001) to an N-th stage (200) brought into N-stage cascade connection and a digital error correction circuit 30 receiving bit data outputs respectively from the first stage (1001) to the N-th stage (200), carrying out digital error correction processing and outputting a final N+1 bit digital signal.
The first stage (1001) receives an analog signal input, converts the analog input signal to 1.5 bit (=2 bit−1), outputs the converted 1.5 bit data to the digital error correction circuit 30 and outputs output voltage derived by doubling residue between the input analog signal and the voltage corresponding with the converted bit data to a stage 2 (not illustrated in the drawing) of the subsequent stage.
The second stage receives an analog signal input output from the first stage (1001), converts the analog input signal to 1.5 bit (=2 bit−1) data, outputs the converted 1.5 bit data to the digital error correction circuit 30 and output voltage derived by doubling residue between the input analog signal and the voltage corresponding with the converted bit data to the second stage (not illustrated in the drawing) of the subsequent stage. Below, in the same ways, each stage undergoes A/D conversion; the N-th stage (200) of the final stage receives an analog signal from the (N−1)-th stage (100N−1), then converts the analog signal voltage to 2-bit data and outputs the 2-bit data to the digital error correction circuit 30.
The digital error correction circuit 30 receives bit data output from the first stage (1001) to the N-th stage (200), sums respective bit data, carries out digital error correction processing and outputs N+1 bit digital signal.
FIG. 14 is a diagram describing a configuration of a stage of the pipeline type A/D converter illustrated in FIG. 12. The function block of the first stage (1001) to the (N−1)-th stage (100N−1) takes the same configuration.
With reference to FIG. 14, each stage of the first stage (1001) to the (N−1)-th stage (100N−1) includes a sample-hold circuit (S/H) 101, a subtraction circuit 102, an amplifier circuit 103, an A/D converter circuit (abbreviated as “ADC”) 104 and a D/A converter circuit (abbreviated as “DAC”) 105. In the N-th stage (200), analog signals do not have to be output to the subsequent stage and, therefore, preferably includes at least only a flash type A/D converter as illustrated in FIG. 18.
In FIG. 14, the sample-hold circuit 101 samples an analog signal Vin from the preceding stage to retain voltage thereof. The A/D converter circuit 104 converts the analog signal Vin to 1.5 bit data and outputs the converted bit data to the digital error correction circuit 30.
The D/A converter circuit 105 converts the data having undergone digital conversion to an analog signal with the A/D converter circuit 104.
The subtraction circuit 102 subtracts the analog signal output from the D/A converter circuit 105 from the input analog signal retained in the sample-hold circuit 101 and outputs the subtraction result (residue signal).
The amplifier circuit 103 causes the residue signal output from the subtraction circuit 102 to undergo voltage amplification at amplification factor of 2 and output the amplified voltage to a stage of the subsequent stage. Such a configuration enables the voltage range of the input analog signal to fall within the range of the same voltage-width (voltage range between +Vref and −Vref, for example) in each stage.
FIG. 16 is a diagram illustrating a configuration of the A/D converter circuit 104 (see FIG. 14) of each stage of the first stage (1001) to the (N−1)-th stage (100N−1). With reference to FIG. 16, the A/D converter circuit 104 is configured as a flash type A/D converter circuit comprising two comparators comparing analog signals with the respective reference potential in parallel. That is, the A/D converter circuit 104 comprises a comparator 110.1 comparing voltage of analog signals with the first reference potential and outputting B1 as a result of comparison, a comparator 110.2 comparing voltage of analog signals with the second reference potential and outputting B0 as a result of comparison and a coder 112 receiving an input of comparison results B0 and B1 from the comparators 110.1 and 110.2 to code the input to 1.5 bit data (D0 and D1). Here, in the case where the voltage range of the input analog signal, that is, the voltage range of the input analog signals to the comparator in each stage falls within the range between +Vref to −Vref, +Vref/4, for example, is selected as the first reference potential and −Vref/4, for example, and the like are selected as the second reference potential. Each stage is configured to input the analog signal obtained by causing the residue signal (balance between the output of the sample-hold circuit 101 and the output voltage of the DAC 105) to undergo voltage amplification at amplification factor of 2 to the stage of the subsequent stage. Therefore, the value of the reference potential of the comparator 110.1 is the same as the value of the reference potential of the comparator 110.2 between the respective stages.
As described above, FIG. 18 is a diagram illustrating an example of a configuration of the N-th stage (200). With reference to FIG. 18, the N-th stage (200) is configured as a flash type A/D converter circuit comprising three comparators for comparing the input analog signals in parallel. That is, the N-th stage comprises a comparator 111.1 comparing voltage of analog signals with the first reference potential and outputting B2 as a result of comparison, a comparator 111.2 comparing voltage of analog signals with the second reference potential and outputting B1 as a result of comparison, a comparator 111.3 comparing voltage of analog signals with the third reference potential and outputting B0 as a result of comparison and a coder 113 receiving inputs of comparison results B0, B1 and B2 from the first to third comparators 111.1 to 111.3 to code the input to two bit data (D0 and D1) and output the digital signals. Here, in the case where the voltage range of the input analog signal, that is, the voltage range of the input analog signals to the comparator in each stage falls within the range between +Vref to −Vref, +Vref/2, for example, is selected as the first reference potential, 0, for example, is selected as the second reference potential and −Vref/2, for example, and the like are selected as the third reference potential.
FIG. 20A illustrates residue plots in each stage. The axis of abscissae is for the analog signal Vin (see FIG. 14) input to the i stage (here, 1≦i≦N−1) and the axis of ordinates is for analog signal Vout (see FIG. 14) output from the stage. Both of Vin and Vout fall within the rage between +Vref and −Vref. FIG. 20A exemplifies residue plots in the case where there is no offset for a comparator of the i-th stage and FIG. 20B exemplifies residue plots in the case where there are offsets ΔVcomp1 and 2 in the comparators to be compared with +/−Vref/4 in voltage, respectively (see Non-patent document 1).
In the pipeline type A/D converter, digital output code of each stage is provided with redundant bit and thereby the offset tolerance of the comparator is alleviated. For example, in a pipeline type A/D converter with resolution of each stage being 1.5 bit, the case where the comparator discriminates the analog signal to be +Vref/4 and −Vref/4, the offset value of the respective comparators up to +Vref/4 and −Vref/4 is permitted since monotonicity of the A/D converter is secured (see Non-patent document 1 and the like).
FIG. 13 illustrates a general configuration of a pipeline type A/D converter as reference. With reference to FIG. 13, the first stage (100a1) to (N−1)-th stage (100aN−1) outputs digital data signal of (B1+1) bit-1 to (BN−1+1) bit-1 and the N-th stage (200a) outputs the digital data signal of BN bit. B1 to BN−1 are respectively predetermined integers being not less than 1. Here, configuration in FIG. 12 corresponds to the case of B1 to BN−1 being 1 and BN being 2 in FIG. 13. FIG. 15 is a diagram illustrating a configuration of the first stage (100a1) to the (N−1)-th stage (100aN−1). In the first (100a1) to the (N−1)-th stage (100aN−1), an ADC circuit 104a outputs a digital signal of (B+1) bit-1 and the voltage amplification factor of the amplifier circuit 103a is set to 2B. FIG. 17 is a diagram illustrating a configuration of the ADC circuit 104 in FIG. 15. With reference to FIG. 17, the ADC circuit 104a is configured by comprising (2B+1−2) units of comparators 100a.1 to 110a.3 in parallel. A coder 112a receiving inputs of the outputs of the comparators 110a.1 to 110a.3 outputs a digital output of (B+1) bit-1. FIG. 19 is a diagram illustrating a configuration of the N-th stage (200a) in FIG. 13. With reference to FIG. 19, the N-th stage (200a) is configured by comprising (2B−1) units of comparators 111a.1 to 111a.3 in parallel. A coder 113a receiving inputs of the outputs of the comparators 111a.1 to 111a.3 outputs a B bit (B=BN in the case of FIG. 13) output.
[Patent Document 1] Japanese Patent Application Laid-Open No. 2005-72844
[Non-Patent Document 1] P. R. Gray “A 10 b 20 Msample/s, 35 mW Pipeline A/D Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 30, No. 3, 1995/March
[Non-Patent Document 2] Byung-Moo “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 38, No. 12, 2003/December
The above described conventional pipeline type A/D converter has problems described below.
(A) Since one comparator influences a wide range of digital output code, in the case where the offset value of the comparator occasionally exceeds the tolerance, the comparator will no longer fulfill required properties as an A/D comparator dramatically.
(B) In the case where the comparator causes an error, the comparator cannot correct the error.
(C) in the case where decrease in the voltage range of the analog signal input to the A/D converter due to drop of the power supply voltage and establishment of multi-bit pipeline stage and the like reduce allowance offset value (offset margin) of the comparator, it becomes difficult to realize a comparator circuit required to secure a required yield factor. Due to decrease in allowance offset value of the comparator, the yield factor of the comparator decreases (occurrence frequency of the offset error in the comparator increases) and the yield factor of the A/D converter decreases.
(D) In the case of shortening the gate length of an MOS transistor for reducing circuit area and speeding up the comparator, the offset value is apt to increase to hardly enable realization of a comparator circuit required for securing a required yield factor.
Due to principles of pipeline type A/D converters, the offset value of a comparator cannot exceed the tolerance. The comparator is configured with a latch circuit to become a positive feedback circuit and is therefore highly sensitive to dispersion in manufacturing such as manufacturing process, shape and the like. Dispersion in manufacturing tends to increase as size reduction progresses. In addition, reduction in circuit area is pondered to enlarge influence of dispersion in manufacturing due to generally called Pelgrom's rule.
Therefore, in the case where a offset canceling technique with capacitance and a offset reducing technique with preamplifier cannot be utilized for application requiring a comparator with low area and low power consumption, it becomes necessary to design a comparator with a yield factor of not less than 3σ. Therefore, circuit designing becomes difficult and realization of accuracy, stability and reliability of operation property of a pipeline type A/D converter becomes difficult.